Improvement in Retention Time of Capacitorless DRAM with Access Transistor

In this paper, we propose a Junctionless (JL)/Accumulation Mode (AM) transistor with an access transistor (JL in series with JL/AM transistor) based capacitorless Dynamic Random Access Memory (1TDRAM) cell. The JL transistor overcomes the problem of ultrasharp p-n junction associated with conventional Metal-Oxide-Semiconductor (MOS) in nanoscale regime. The access transistor (AT) is utilized to reduces the leakage, and thus, improves the Retention Time (RT) and Sense Margin (SM) of the proposed capacitorless DRAM cell. Thus, the proposed DRAM cell achieved a maximum SM of ~4.6 {\mu}A/{\mu}m with RT of ~6.5 s for a gate length (Lg) of 100nm. Further, this topology shows better gate length scalability with a fixed gate length of AT and achieves RT of ~100 ms and ~10 ms for a scaled gate length of 10 nm at 27 {\deg}C and 85 {\deg}C, respectively

Device and circuit performance analysis of double gate junctionless transistors at L(g) = 18 nm

The design and characteristics of double-gate (DG) junctionless (JL) devices are compared with the DG inversion-mode (IM) field effect transistors (FETs) at 45 nm technology node with effective channel length of 18 nm. The comparison are performed at iso-V(th) for both n- and p-type of devices. The JL device shows lower drain-induced barrier lowering, steep subthreshold slope and lower OFF state current. For the first time, the authors demonstrate a pass gate (PG) logic, inverter circuit and static random access memory (SRAM) stability analysis using JL devices, rather than a complementary metal-oxide semiconductor (CMOS) configuration. They observed that transient response of JL PG configuration is similar to that of conventional CMOS PGs. JL inverter also shows similar transient characteristics with 25% reduction in delay and 12% improvement in 6 T SRAM cell stability compared with IMFETs, which shows large potential in digital circuit applications. The simulations were performed using coupled device-circuit methodology in ATLAS technology aided computer design (TCAD) mixed-mode simulator